We're building verification infrastructure from scratch for high-performance RISC-V CPU clusters and SoCs. This role owns the system-level DV strategy, verifying how multiple IPs interact across caches, NoCs, coherence protocols, and memory hierarchies. You'll define verification plans, architect UVM environments, and drive coverage closure for features that span the entire cluster. If you think in terms of systems, not just blocks, and want to shape methodology on a ground-up CPU program—this is it.

This is a hybrid role in Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You thrive building robust verification environments using SystemVerilog, UVM, and C++ and can define and drive verification plans independently.
• System-level mindset, with experience integrating multiple IPs into clusters or SoCs and verifying their interactions.
• You have a strong grasp of stimulus planning, debug techniques, and coverage closure for complex hardware subsystems like caches, NoCs, and memory hierarchies.
• Comfortable working on features that span multiple IPs—such as coherence and security—and ensuring their correct behavior at the cluster or SoC level.

What We Need

• Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field.
• Strong experience with SystemVerilog and UVM-based verification.
• Proven ability to drive subsystem or SoC-level DV projects with integration and system feature validation responsibilities.
• Familiarity with AXI/CHI protocols, system IP flows (debug/trace, power management), and integration flows for multi-IP verification environments.

What You Will Learn

• Techniques to scale DV infrastructure for verifying high-performance RISC-V clusters and SoCs.
• How to verify multi-agent interactions across CPUs, system IPs, and NoC or fabric components.
• Best practices for cross-IP feature convergence, integration-level planning, and reuse across cluster/SoC programs.
• How to collaborate with global teams across RTL, DV, software, and validation for cohesive system-level bring-up.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.