Senior IP Design Verification Engineer
- 755 Intel Microelectronics (M) Sdn. Bhd.
- US, California, Santa Clara
- 7mo ago
- Full-Time
- On-site
Do Something Wonderful!
Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Who We Are
Become a key member of a team participating in the Integration and Verification of a future Intel CPU. This position requires and Engineer with broad Physical Design and Static Timing Analysis skills, coupled with leadership skills necessary to drive methodology and to collaborate effectively with multiple functional teams within the CPU design team.
Who You Are
Responsibilities may include but are not limited to:
Performs functional verification of IP logic to ensure design will meet specification requirements.
Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm microarchitecture specifications.
Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
Replicates, root causes, and debugs issues in the presilicon environment.
Finds and implements corrective measures to resolve failing tests.
Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.
Maintains and improves existing functional verification infrastructure and methodology.
Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must have a Bachelor’s Degree in Computer Engineering/Computer Science or Electrical Engineering with 4+ years of relevant experience -OR- a Master’s Degree in Computer Engineering Computer Science or Electrical Engineering with 3+ years of relevant experience with C and Object-Oriented Software design including algorithms and data structures -OR- PhD in Computer Engineering/Computer Science or Electrical Engineering
Preferred Qualifications
Proficiency in System C System Verilog UVM and ESL modeling methodologies
Proficiency in HW design and verification methodologies
Working knowledge of highspeed HW protocols eg PCIe UPI DDR
Knowledge of Software development practices and quality standards
Experience with Unix Windows based SW development tools.
Experience developing bus functional models for unit level verification or Verification IP development
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
Annual Salary Range for jobs which could be performed in the US:
$139,710.00-262,680.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.