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How You Will Contribute:

As a Test Development Engineer at Ciena, you will play a key role in designing and implementing production test solutions for analog blocks within our advanced SoC ASICs of Wavelogic product line. Your responsibilities will include developing and maintaining digital test environment infrastructure, utilizing C and SystemVerilog code, and collaborating closely with chip designers, test development architects, and external test houses.

This position requires a strong blend of hardware and software skills to create high-quality test programs for cutting-edge ASICs. You will write C/C++ and SystemVerilog code, build test cases, innovate, automate integrated circuit (IC) tests, and troubleshoot issues to ensure the successful production of our Wavelogic ASICs.

Your contributions will include:

• Collaborating with analog designers, digital designers, digital verifiers, and analog DFT advisors to create a verification test plan.
• Working with digital and analog design primes, digital verification primes, and senior DFT advisor to validate in simulation on-die test infrastructure before releasing the netlist to layout.
• Participating in design reviews and providing testability feedback.
• Developing reliable testbenches, regressionable test cases, scripts, and programs and algorithms based on analog specifications.
• Debugging and troubleshooting test failures to identify root causes.
• Building and automating workflows through scripting for increased productivity and efficiency.
• Assisting in the development and release of ATE test programs for mass production.
• Assisting the test house in validating imported test cases on the ATE for package and wafer testing.
• Optimizing test solutions to improve yield and reduce test time.
• Participating in test data analysis to ensure accurate and repeatable test coverage.
• Staying updated with emerging testing technologies and methodologies.
• Coordinating and delivering concise status reports at various stages of development.

If you thrive in a collaborative environment, enjoy problem-solving, and possess solid understanding of analog blocks (e.g. DACs, ADCs, PLLs, ...) and programming proficiency in C++ and Verilog, this position offers an exciting opportunity to innovate and contribute to state-of-the-art test solutions. Join us at Ciena and help shape the future of ASIC testing.

The above lists are intended to describe the general nature and level of work, and they are not intended to be a comprehensive list of all responsibilities, duties and skills required to be qualified and to be performed by the selected candidate. You will have an opportunity to better understand the role through the interview experience.

The Must haves:

• Minimum Bachelor’s degree in Electrical or Computer Engineering coupled with practical experience in the use of System Verilog, UVM, SVA, C/C++ and simulators from major vendors.
• Knowledge of digital and analog DAC/ADC/PLL test techniques.
• Practical experience developing scripts to automate tasks.
• Knowledge of high-speed and mixed-signal ASICs
• Good communication skills
• Ability to Multitask among multiple projects.

Assets:

• Knowledge of Integrated Circuit testing on ATE platforms such as the Advantest V93000
• Using Jira for bug tracking and GIT for source code management and revision tracking
• Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++.

Pay Range: The annual salary range for this position is $100,900 - $161,100.

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At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard.  Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.