CPU RTL Design Engineer
- Samsung Austin Semiconductor, LLC.
- 4mo ago
- Full-Time
- On-site
Position Summary
About Samsung Semiconductor India Research (SSIR)Role and Responsibilities
Roles and Responsibilities
Job Description:
We are looking for a highly skilled and motivated RTL Design and Validation Engineer to join our team, focusing on the development of cutting-edge CPU cores.
In this role, you will be responsible for the subsystem architecture, design, and functional verification of different CPU cores used in an SoC, ensuring the delivery of high-quality, high-performance silicon products.
A strong understanding of modern CPU architectures, with specific experience in RISC-V or ARM cores, is highly valued.
Key Responsibilities
Microarchitecture & Design: Drive the microarchitecture definition and RTL design of complex CPU subsystem, with system level understanding of CPU of various configurations and interfacing with other domains.
RTL Coding: Implement synthesizable RTL code using Hardware Description Languages (HDL) such as Verilog and SystemVerilog, adhering to design specifications and quality standards.
Verification Support: Collaborate closely with the verification team to develop test plans, support functional simulation and debugging of test cases, and ensure design compliance.
Optimization: Optimize the CPU and subsystem for power, performance, area (PPA), and timing goals, working with physical design engineers to address constraints.
Documentation: Create and maintain detailed design specifications, microarchitecture documents, and test plans.
Collaboration: Partner with cross-functional teams including architecture, physical design, and software teams throughout the entire chip development lifecycle, from concept to post-silicon validation.
Required Qualifications
Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Experience: 4 to 10 years of proven experience in digital IC design or RTL design, with good understanding of CPU architectures (RISC-V or ARM).
Technical Skills:
Proficiency in Verilog and/or SystemVerilog.
Strong understanding of digital design principles, computer architecture, and synchronous design methodologies.
Familiarity with standard bus protocols like AMBA AXI, AHB, and APB.
Experience with industry-standard EDA tools for simulation (e.g., Xcelium, VCS), synthesis (e.g., Synopsys Design Compiler), and timing analysis.
Familiarity with scripting languages such as Python, Perl, or Tcl for automation tasks.
Good to Have Experience
Experience with designing or validating RISC-V or ARM CPU cores, including knowledge of their microarchitecture and instruction sets.
Hands-on experience with specific CPU features such as cache coherence, memory management units (MMU), and branch prediction.
Exposure to formal verification methods and coverage-driven verification (CDV) using methodologies like UVM.
Experience with FPGA prototyping and emulation platforms for pre-silicon validation
Disclaimer
Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
Skills and Qualifications
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