At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Join the Digital & Signoff Group (DSG) at Cadence and contribute to the development of the Genus Synthesis Solution, a state-of-the-art logic synthesis tool that optimizes Power, Performance, and Area (PPA) for advanced digital ASICs. This internship offers hands-on experience in software development for EDA tools, working closely with R&D and product engineering teams in a collaborative, innovation-driven environment.

Responsibilities

• Design, implement, troubleshoot, and debug software programs on Unix/Linux platforms.
• Develop and enhance algorithms for logic synthesis and physical design flows.
• Validate new synthesis features and ensure correctness and optimal configurations.
• Assist with customer support by analyzing tool usage and providing feedback to R&D.
• Contribute to documentation, including Product Requirement Specifications (PRS) for new features.

Required Qualifications

• Currently pursuing a PhD in Computer Science, Electrical Engineering, or Computer Engineering.
• Strong programming skills in C/C++; exposure to Python and Tcl is a plus.
• Solid understanding of data structures, algorithms, and object-oriented programming.
• Familiarity with logic synthesis, physical design, and timing analysis.
• Experience with Unix/Linux environments.
• Excellent analytical and problem-solving skills; strong communication abilities.

The annual salary range for California is $28.60 to $53.12 an hour. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid holidays and 401(k) plan with employer match.

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